**S RIVATSAN RAVEENDRAN**
Sunnyvale, CA
LinkedIn: linkedin.com/in/srivatsan-raveendran
Phone: 646-684-9502
Email: srivatsanrr09@gmail.com

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### **EDUCATION**
**Columbia University**
New York, NY
*Master of Science, Computer Engineering*
GPA: 4.02/4.0 (4.0 is A and >4 is A+)
*Dec 2022*
Relevant Coursework: Modeling and Performance Evaluation of Systems, Computer Architecture, System-on-Chip Platforms, Formal Verification

**Vellore Institute of Technology**
Vellore, India
*Bachelor of Technology, Electronics and Communication Engineering*
GPA: 9.48/10.0
*Jul 2021*
Relevant Coursework: Microcontroller and Embedded Systems, Networking Fundamentals, Electronic Circuits, Sensors and Instrumentation

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### **SKILLS**
C, C++, Python, Ethernet, TCP/IP, Linux, FPGA, Embedded Systems, RTOS, Git, CAN, Verilog, CPU Performance Optimization, Software Design Principles, Multi-core/Multi-threaded Environments, Software Testing, Integration, Oscilloscopes, Logic Analyzer, Polarium, JIRA, JTAG Debugger, VLAN, DMA

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### **EXPERIENCE**
**Tesla**
Palo Alto, CA
*Software Integration Engineer - Firmware System Architecture*
*Feb 2023 - Present*
- Led power optimization strategy for microcontroller chips using TC-10 protocol, reducing power consumption by 75W per vehicle, enabling ~300 additional cars/month.
- Improved firmware performance for Ethernet frame processing, frame deduplication algorithms, and implemented real-time diagnostics.
- Identified and resolved race conditions during PHY access from drivers.
- Designed next-gen automotive Ethernet communication architecture for Cybertruck, optimizing firmware for 15% latency reduction and 10% CPU utilization improvement.
- Ran Interface Change Control Board (CCB) to analyze system problems across vehicle ECUs.

*System Firmware Development Intern, Firmware Systems Architecture*
*May 2022 - Aug 2022*
- Designed interrupt-based CAN error diagnostics for PowerPC and STM microcontrollers.
- Developed RTOS-based firmware to reduce jitter to 1ms for safety-critical communications.

**Columbia University**
New York, NY
*Research and Teaching Assistant, System Level Design Group*
*Sep 2022 - Dec 2022*
- Integrated open-source RISC-V GPU into SoC using AXI4 and APB interfaces, boosting data transfer speed by 20%.
- Optimized CPU-GPU communication at network-on-chip interface, reducing latency.
- Designed High-Level Synthesis CNN Accelerator with 15% area reduction.

**Indian Tobacco Company (ITC) Limited**
Chennai, India
*Summer Intern (Research Collaboration)*
*May 2019 - Jul 2019*
- Designed AI-based high-aspect-ratio object sorting machine, doubling throughput with low latency.
- Optimized processor performance with NVIDIA TensorRT (Patent 2024).

**Samsung Prism Developer**
Bangalore, India
*Samsung Prism Project (Research Collaboration)*
*Nov 2019 - Nov 2020*
- Developed CPU-GPU partitioning for neural networks using ARM NN SDK for TensorFlow/Caffe backends.
- Analyzed parser library for modifications targeting ARM-A series processors.

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### **PROJECTS**
**Continental Automotive Hackathon: Passenger Crash Safety System with Advanced Driver Assistance**
*Nov 2019 - Dec 2019*
- Engineered vision-based ADAS to mitigate crashes (1st Prize, featured in Autocar).
- Developed 2-stage algorithm with object detection & Kalman Filters for speed estimation.

**Volvo Adventure, UNEP & UNESCO International Conference**
*Jan 2013 - Jul 2013*
- Led global power optimization initiative (Top 7 teams globally).
- Awarded Tunza Award for potential CO2 reduction by 8M K-Tons.

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### **PATENTS & PUBLICATIONS**
- *Patent:* Vision-based inspection device for automation of sorting high-aspect-ratio objects (Granted 2024).
- *Patent:* Intelligent system for flood control & rapid action (Published 2020).
- *Elsevier:* Inspecting MEMS substrate failures using computer vision (Dec 2021).
- *Springer:* Machine Learning model for predicting COVID-19 susceptibility (2020).

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